Dynamic Random Access Memories (DRAMs) are used in a variety of applications. It is a very popular memory technology because of its high density and consequent low price. FIG. 1 shows a simplified structure of a DRAM chip 100. The chip 100 comprises a plurality of memory cells 102. Each memory cell comprises a storage capacitor 102a and an access transistor 102b. One memory bit is stored in each memory cell 102. The value of the memory bit is represented by voltage stored in the storage capacitor 102a. A logic high is stored as a high voltage (Vdd), while logic low is stored as a low voltage (typically ground).
The memory cells 102 are arranged on the chip 100 in a grid of rows and columns. Each row is a word line 104a-104b, and each column is a bit line 106a-106b. A single memory cell can be selected by a row address and a column address. Row address decoders 108 and column address decoders 110 process their respective addresses such that the correct row and column is accessed to select a particular cell. The grid organization of memory cells and its row and column address decoders are well known in the art and will not be further discussed here. Sense amplifiers 114a and 114b detect the charges stored on cells 102 in its column 106a and 106b, respectively.
A feature of DRAM is the destructive nature of the readout procedure. For example, if Cell 112 is to be read. The cell's 112 word line 104a is selected. The charge from the storage capacitor 102a of cell 112 is then transferred to the sense amplifier 114b, which detects it as either a "1" (logic high) or a "0" (logic low) to provide the readout of the cell. This readout procedure is destructive, since it disturbs the information in the storage capacitor 102a. Thus, the read operation is followed by a subsequent sensing and writing operation to refresh the information back into the cell 112, using write-back circuitry.
This refresh operation involves utilizing the sense amplifier 114b to compare the charge from the storage capacitor 102a of cell 112 to a "reference voltage" stored on certain memory cells, called "reference cells" (not shown). If the charge from the storage capacitor 102a of cell 112 is higher than the reference voltage, then the sense amplifier 114b will interpret the charge as a "1" and restore a charge of Vdd to the storage capacitor 102a of cell 112. If the charge from the storage capacitor 102a of cell 112 is lower than the reference voltage, then the sense amplifier 114b will interpret the charge as a "0" and restore a ground to the storage capacitor 102a of cell 112.
A problem of great concern is the gradual leakage of charge from the storage capacitors causing memory cells of the DRAM to eventually lose their information. Due to the leakage current of the memory cells, charge will leak from a memory cell storing a "1", and a memory cell storing a "0" will collect charge. To preserve the information, the charge in the memory cells must be refreshed periodically to charge "1"s in the memory cells back to full Vdd and discharge "0"s in the memory cells back to ground. The refresh process is periodically performed by providing a read operation as explained above with the selection of each word line without the selection of a bit line.
FIGS. 2A-2B show a conventional reference cell structure 200 which had been widely used in the DRAM industry. FIG. 2A shows the circuitry of this structure 200 while FIG. 2B shows the timing diagram for this circuitry. In this structure, each memory cell 210 (comprising a storage capacitor 210a and an access transistor 210b) is attached to a wordline 214, a bit line 202, and a complementary bit line 204. For this cell structure, both the bit line 202 and the complementary bit line 204 were precharged to full Vdd before sensing by the sense amplifier 212 began. A reference voltage of one-half of Vdd was stored on the storage capacitor 206a of the reference cell 206 on the reference word line 208. The reference cell 206 also comprises access transistor 206b. A one-half Vdd was stored on storage capacitor 206a by making its area half of the area of the storage capacitor 210a. This was extremely difficult when the memory cell 210 became as small as they are in the current state of the art. Thus, the size of memory cells in current DRAM has become too small for this method to be practical. Also, this conventional method required an additional precharge device for the storage capacitor 206a of the reference cell 206 which caused design difficulties.
FIGS. 3A-3B show another conventional reference cell structure 300. FIG. 3A shows the circuitry for this structure 300 while FIG. 3B shows its timing diagram. This structure 300 solved one of the problems of the structure 200 in FIG. 2A. Storage capacitor 302a and access transistor 302b comprise the memory cell 302, on the word line 314 while storage capacitors 304a and 306a and access transistor 304b 306b comprise the reference cells 304 and 306. Here, the storage capacitors 302a, 304a and 306a have the same area. Thus, there was no need for an additional precharge device. This device precharged the bit line 308 and complementary bit line 310 to one-half Vdd. This structure too became problematic as memory cells became smaller because of the limitations of the sense amplifier 312, as explained in conjunction with FIGS. 4A-4B below.
FIGS. 4A-4B show a conventional DRAM sensing structure 400 which can be used with reference cell structure 300 of FIG. 3. FIG. 4A shows the circuitry for the sensing structure 400 while FIG. 4B shows the timing diagram for this circuit. In this device, the equalization device 402 precharges the bit line 404 and complementary bit line 406 to one-half Vdd before a word line 408 is selected for charge sharing. When a word line 408 is selected, charge is shared between the bit line 404 and the memory cell 418 on the word line 408. If the memory cell 418 contains a "1", then the bit line 404 rises to a voltage slightly higher than one-half Vdd. The bit line 404 charges up only slightly because its capacitance is much larger than the capacitance of the memory cell. If the cell contains a "0", then the bit line 404 will fall to a voltage slightly lower than one-half Vdd. The resulting bit line voltage is then transferred to the sense amplifiers 410, 412.
Two kinds of sense amplifiers are used for this structure 400: an NMOS sense amplifier (N-SA) 410 and a PMOS sense amplifier (P-SA) 412. Typically, the NMOS transistors 414a-414b in the N-SA 410 are turned on first due to its high current drivability and its lower threshold voltage than the PMOS transistors 416a-416b in the P-SA 412.
The N-SA 410 compares the bit line's 404 voltage with the complementary bit line's 406 voltage after charge sharing. If the bit line 404 voltage is higher than the complementary bit line 406 voltage, the bottom NMOS transistor 414b of the N-SA 410 is activated, which in turn activates the PMOS transistor 416a, which then triggers a refresh of Vdd to the memory cell 418. If the bit line 404 voltage is lower than the complementary bit line 406 voltage, the NMOS transistor 414a of the N-SA 410 will be activated and will trigger a refresh of a ground voltage to the memory cell 418. Thus, the threshold voltage of the NMOS transistors 414 in the N-SA 410 is very important in the proper operation of DRAM.
Once a refresh operation is performed by the sense amplifiers N-SA 410 and P-SA 412, the equalization device 402 restores the bit line 404 and the complementary bit line 406 to one-half Vdd to wait for the next refresh cycle.
As memory cells become smaller so that more of them may be placed onto a single chip, the conventional sensing structure 400 becomes problematic. The need for a lower voltage operation of DRAMs is increasing every day. The Vdd for current DRAM is 3.3 V. Some memory devices that have memory density over 16 Megabits or 64 Megabits are now using voltage regulators to maintain Vdd as low as 2.2 V-2.4 V. If a Vdd below 2.0 V is used, the threshold voltage for the sense amplifier is set at less than 1.0 V. The bit lines would be precharged to less than 1.0 V. If the bit line shares charge with a memory cell storing Vdd, the resulting bit line voltage would be slightly above 1.0 V. The difference between the bit line voltage and the threshold voltage would only thus be approximately 0.1 V to 0.2 V. Although the NMOS transistors 414a-414b of N-SA 410 are suppose to be activated if the bit line voltage transferred to it is higher than the threshold voltage, due to physical limitations of the transistor devices, a small voltage difference, such as 0.1 V to 0.2 V, between the bit line voltage and the threshold voltage may not be properly detected by the transistors. Accordingly, the result is that the sense amplifiers may not be activated at the proper times. This seriously compromises the reliability of the sense amplifiers, and ultimately the operation of the DRAM. Techniques currently exist to manufacture semiconductors to operate successfully with a threshold voltage much lower than 1.0 V, however, the manufacturing process involved is very expensive and is impractical for most applications.
Thus, there is a need for a method and structure for a refresh operation in a memory device that has a Vdd that is 2.0 V or lower without compromising the reliability of the sense amplifiers. The manufacturing of the structure should be cost effective and practical. The present invention addresses such a need.